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Quartus Prime ̿ нý ǽ - with Verilog HDL


Quartus Prime ̿ нý ǽ - with Verilog HDL

赿 | ǻ

Ⱓ
2020-09-25
뷮
135 K
PCƮºPC
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1, 0, 0
å α׷ ġ ȵǽó?å α׷  ġ
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ֱ ΰ(AI) ġϰ , 뷮 ͸ ȿ ó ִ FPGA 䰡 ϰ ִ. FPGA ʿ信 ȸθ (Programmable) ˰ 踦 ó Ѵ. ̷ ü а迡 ϵ (Hardware Description Language) ϰ ְ, ʿ伺 εǸ鼭 ڴ å ϰ Ǿ.
FPGA ʰ Ǵ ý ǽ Ͽ. ý 迡 , ϵ  ̿ Ϲȭ ǰ ִ. ̷ ϵ ߿ C Verilog HDL ̿Ͽ ȸθ ϰ, ùķ̼ ȸ ϰ, FPGA Ͽ ׽ƮϿ.

ڼҰ

1 Verilog Ұ
2 Modelsim ̿ ùķ̼
3 Intel Quartus Prime ̿ ùķ̼
4 ճȸ
5 ȸ
6 DE0-Nano 带 ̿ ǽ

ټ

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(ѱ 40̳)
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ϵ ϴ.