Quartus Prime ̿ нý ǽ - with Verilog HDL
赿 | ǻ
å α ġ ȵǽó?
ֱ ΰ(AI) ġϰ , 뷮 ȿ ó ִ FPGA 䰡 ϰ ִ. FPGA ʿ信 ȸθ (Programmable) ˰ 踦 ó Ѵ. ̷ ü а迡 ϵ (Hardware Description Language) ϰ ְ, ʿ伺 εǸ鼭 ڴ å ϰ Ǿ.
FPGA ʰ Ǵ ý ǽ Ͽ. ý 迡 , ϵ ̿ Ϲȭ ǰ ִ. ̷ ϵ ߿ C Verilog HDL ̿Ͽ ȸθ ϰ, ùķ̼ ȸ ϰ, FPGA Ͽ ƮϿ.
1 Verilog Ұ
2 Modelsim ̿ ùķ̼
3 Intel Quartus Prime ̿ ùķ̼
4 ճȸ
5 ȸ
6 DE0-Nano 带 ̿ ǽ